Increase in the speed and increase in the degree of integration of an integrated circuit using MOSFETs have been advanced, accompanied by the decrease in the size.
For example, contrarily to the fact that in a 1M D-RAM the smallest channel length is about 1.3 .mu.m, it is possible to realize an MOSFET having a channel length of about 0.1 .mu.m. Although the switching speed of a semiconductor logic circuit is increased together with the decrease in the size, it is said that the working speed thereof is generally lower than that of a logic integrated circuit using bipolar transistors. However the switching speed of the MOSFET increases due to the increase in the mobility and the saturation speed, if the working temperature is lowered from the room temperature (300K) to the liquid nitrogen temperature (77K). Further it is known that the RC time constant in the wiring is decreased by the decrease in the wiring resistance so that the working speed of the integrated circuit using MOSFETs can be as high as the working speed of the integrated circuit using bipolar transistors.
Even if a bipolar transistor is driven at the liquid nitrogen temperature, the switching speed thereof is not increased because of the freeze out in the base layer. Therefore it is difficult to increase the working speed of Si npn or pnp bipolar transistors having the prior art structure by the low temperature operation.
It is known also that, since electric power consumption per gate for the MOSFET integrated circuit is smaller than that for the bipolar transistor integrated circuit, the degree of integration per chip thereof is greater than that of the bipolar transistor integrated circuit. Thus it can be expected to realize a high speed and high density LSI provided with both the high speed of the bipolar transistor LSI and a high degree of integration of the MOSFET LSI by driving an LSI using fine MOSFETs, whose effective channel length is smaller than 1 .mu.m at the liquid nitrogen temperature (77K).
Heretofore it was said that a Josephson logic circuit working at the liquid helium temperature (4.2K) as a low temperature working device or integrated circuit can realize a high speed logic integrated circuit. However, since a Josephson logic element utilizing the superconduction phenomenon works only in the neighborhood of 4.2K and it cannot work at the room temperature, the operation thereof cannot be checked at the room temperature. For example, in the case of constructing a large scale computer, it is not possible to exchange rapidly defective chips or boards and tremendous work and time are necessary. Therefore it is practically impossible to construct any large scale system. Consequently in a system, by which it is tried to obtain a high performance by a low temperature operation, it is necessary that the device or the system can be driven both at the room temperature and at the low temperature, although the working speed is low at the room temperature.
The MOSFETs can be driven essentially from the room temperature to an extremely low temperature of 4.2K and therefore the construction of a large system by using them is easier than by using Josephson elements.
A prior art MOSFET integrated circuit driven at liquid nitrogen temperature is constructed by a complementary type (CMOS) logic circuit, because the threshold voltage thereof does not vary significantly between the room temperature and 77K. However, since a logic circuit of enhancement/depletion structure (hereinbelow called E/D structure) can be constructed only by n channel MOSFETs, the fabrication process therefor is easier than that for the CMOS logic circuit, for which it is required to integrate p channel MOSFETs and n channel MOSFETs on a same substrate. Further, since an NAND or NOR circuit having n inputs is constructed by 2n MOSFETs by the CMOS structure, contrarily to the fact that it is constructed by (n+1) MOSFETs by the E/D structure, in the case where a same logic circuit is constructed, the E/D structure has an advantage that it can be constructed by less MOSFETs than the CMOS structure.
Consequently, if a logic circuit of E/D structure can be constructed in a so small size that the channel length thereof is smaller than 0.5 .mu.m and driven stably both at the room temperature and at the liquid nitrogen temperature, a ultra-high speed ultra-high density integrated circuit provided with both the high speed of the bipolar transistor and the high density integration of the MOSFET can be realized by a relatively simple process, as described previously.
However an MOSFET logic circuit of prior art E/D structure had following problems and could not exhibit the characteristics described above.
FIG. 7(A) shows an example of the prior art inverter circuit of E/D structure, in which reference numeral 1 is an input terminal; 2 is an output terminal; 3 is a source terminal; 4 is a depletion type n channel MOSFET; 5 is an enhancement type n channel MOSFET; and 6 is the ground. Since a logic integrated circuit or a memory integrated circuit is constructed by a modification of an inverter, such an inverter as described above is the basic unit of the integrated circuit. Since, in general, in Si the mobility of electrons is greater than the mobility of holes, n channel MOSFETs, by which a high speed operation is possible, are used. In the following explanation the case where n channel MOSFETs are used is taken as an example. FIG. 7(B) shows an example of output characteristics of the inverter.
In the operation of the inverter circuit indicated in FIG. 7(A), when the voltage in the input voltage V.sub.in applied to the input terminal 1 is sufficiently lower than V.sub.IN V, a voltage, which is approximately equal to the source voltage V.sub.DD applied to the source terminal 3, is produced at the output terminal 2. When a voltage, which is approximately equal to the source voltage V.sub.DD, is applied as the input voltage V.sub.in, the output voltage V.sub.out has a level almost equal to zero. In practice the level is not at zero, but a slight voltage V.sub.LOW is produced. Usually the voltage V.sub.LOW is about 1/10 of the source voltage V.sub.DD.
Concerning the characteristics S.sub.E and S.sub.D of the enhancement type n channel MOSFET and the depletion type n channel MOSFET, as indicated in FIG. 8, the gate voltage (threshold voltage) V.sub.th, by which the drain current I.sub.D begins to flow, when the gate voltage V.sub.G is applied, is positive (V.sub.th.sup.E) for the enhancement type and negative (V.sub.th.sup.D) for the depletion type.
In order to realize the inverter operation as indicated in FIG. 7(B), the threshold voltages V.sub.th.sup.E and V.sub.th.sup.D of the enhancement type and the depletion type MOSFET constituting the inverter is designed so as to be about 0.2 V.sub.DD and -0.6 V.sub.DD, respectively. FIG. 9 is a cross sectional view of an example of the MOSFET inverter of E/D structure indicated in FIG. 7(A).
In the MOSFET indicated in FIG. 9 the element isolation is effected by using the known LOCOS isolation method.
In the figure, reference numeral 7 is a p conductivity type Si substrate; 8 is a field oxide film; 9 is a p.sup.+ doped region (channel stopper); 10 is an n.sup.+ doped region (acting as the source region S of the enhancement type MOSFET); 11 is another n.sup.+ doped region (acting as the drain region D of the enhancement type MOSFET and the source region S of the depletion type MOSFET formed in a same region); 12 is still another n.sup.+ doped region (acting as the drain region D of the depletion type MOSFET); 13 is a gate insulating film for the enhancement type MOSFET; 14 is a gate electrode for the enhancement type MOSFET; 15 is a channel doped region of the enhancement type MOSFET doped with impurities of same conductivity as the p conductivity type Si; 16 and 17 are a gate oxide film and a gate electrode for the depletion type MOSFET, respectively; 18 and 18' are channel doped regions of the depletion type MOSFET doped with impurities of conductivity type opposite to the p conductivity type Si; 19 is a PSG film (insulating film); 20 is an electrode connected electrically with the gate electrode 16 for the depletion type MOSFET; 21 is an Al metal wiring (ground line); 22 is an Al metal wiring (source line); 23 represents the channel length of the enhancement type MOSFET; and 24 represents the channel length of the depletion type MOSFET.
The gate electrodes 14 and 17 are made of n.sup.+ polycrystalline silicon. Ions of impurities such as B, etc. having the same conductivity type as the p conductivity type Si substrate 7 are implanted in the channel doped region 15 just below the gate oxide film 13 for the enhancement type MOSFET to adjust the threshold voltage V.sub.th.sup.E of the enhancement type MOSFET so as to be about 0.2 V.sub.DD with respect to the source voltage V.sub.DD. P or As ions, which are impurities having the conductivity type opposite to the p conductivity type Si substrate 7 are implanted in the channel doped region 18 just below the gate oxide film 16 for the depletion type MOSFET to adjust the threshold voltage V.sub.th.sup.D of the depletion type MOSFET so as to be about -0.6 V.sub.DD with respect to the source voltage V.sub.DD.
The electrode 20 connected electrically with the gate electrode 17 for the depletion type MOSFET is extended in a plane perpendicular to the sheet. The electrode 20 is made of the same material as the gate electrode for the depletion type MOSFET, i.e. n.sup.+ polycrystalline Si. The source of the depletion type MOSFET and the drain of the enhancement type MOSFET are connected with the n.sup.+ region 11 through the electrode connected electrically with the gate electrode 17 for the depletion type MOSFET. The electrode 20 serves as the output terminal 2 of the inverter circuit indicated in FIG. 7(A).
FIG. 10 shows schematically the energy band in the part of gate electrode G/oxide film OX/p-Si substrate S of an enhancement type MOSFET. The figure shows a case where as positive voltage is applied to the gate electrode and an n type inversion layer as well as ionized acceptor atoms AT are formed.
Since the enhancement type MOSFET forms an n type inverted layer in the surface portion of the Si substrate by bending electrically the forbidden band in the surface portion of the p conductivity type Si substrate by the voltage applied to the gate electrode, both at the room temperature and at the liquid nitrogen temperature it performs the enhancement type operation, i.e. the threshold voltage V.sub.th.sup.E remains positive.
FIG. 11 shows schematically the energy band in the part of gate electrode G/oxide film OX/p-Si substrate S of a prior art depletion type MOSFET, in which ions such as P, As, etc., which are impurities of conductivity type opposite to that of the p conductivity type Si substrate, are implanted. At the room temperature, since there exist electrons EL due to ionization of As or P just below the gate oxide film, the MOSFET described above performs the depletion operation. In the figure IO indicates P or As atoms, with which the channel is doped, which are ionized at the room temperature. However, at 77K, as indicated by IOin FIG. 12, since As or P implanted as opposite conductivity type impurities is frozen out and not ionized, in the case where no gate voltage is applied, no n channel layer is formed just below the gate oxide film 16 and therefore it does not perform the depletion operation. That is, the MOSFET, which can perform the depletion operation owing to the implanted impurities of opposite conductivity type, performs the enhancement operation at the liquid nitrogen temperature.
Consequently, there was a problem that although the prior art inverter of E/D structure using depletion type MOSFETs including the channel portion 18' doped with the impurities of opposite conductivity type performs the normal operation at the room temperature, it cannot perform the normal operation at the liquid nitrogen temperature.
In the above explanation, no absolute value of the source voltage V.sub.DD for the inverter or the MOSFET is dealt with. Heretofore the source voltage for the MOSFET was determined at 5 V, in order to hold the interchangeability with TTL. However, if the source voltage is kept at 5 V, for an MOSFET having a channel length smaller than 1 .mu.m, the electric field strength within the element is increased. Thus it has become more and more difficult to secure the normal operation and the reliability of the MOSFET because of hot carrier deterioration and drain break down. Consequently, the source voltage for the integrated circuit cannot help being decreased. For example, in the case of a channel length of 0.5 .mu.m, it is estimated to be about 3.3 V and in the case of a channel length of 0.1 .mu.m, it is estimated to be about 1 to 1.5 V.
Therefore, since in the high speed and high density MOSFET, which is the subject of the present invention the channel length is necessarily smaller than 1 .mu.m, the magnitude of the threshold voltage V.sub.th.sup.D should be about -2 V when the source voltage V.sub.DD =3.3 V and about -0.6 to 0.9 V when V.sub.DD =1 to 1.5 V.
The MOSFET logic circuit of E/D structure is characterized in that the fabrication process is easier and the number of MOSFETs at constructing a same logic circuit is smaller with respect to the logic circuit of CMOS structure.
The working speed of the logic circuits remains almost equal both for the E/D structure and for the CMOS structure and it is possible also therefor to increase the working speed by the operation at the liquid nitrogen temperature. However, as described previously, the inverter of E/D structure using depletion MOSFETs, in which the channel is doped with impurities of conductivity type opposite to the conductivity type of the used semiconductor substrate, has a drawback that it cannot perform the depletion operation at the low temperature, because the impurities are frozen out at that time.